Design and Implementation of a Synchronous AHB to APB Bridge in System-on-Chip Applications

Abstract

The requirement of effectively combining key units in an integrated system is proliferating. SoC system is developed to provide a chip-level integration, which become the inevitable trend of integrated circuit development and is widely used in smartphones, industrial applications, and microcontrollers. The ARM AMBA protocol works as a universally adopted way of interaction between various parts of the system. In AMBA architecture, the AHB to APB bridge significantly contributes to combining the high-performance AHB bus and low-power APB bus in the SoC system. This project is to implement an AHB to APB bridge using Verilog, enabling stable data transfer between these two buses. The proposed AHB to APB bridge is intended to fit different read or write strategies and ensure the proper working of the peripherals on the APB bus. The bridge has been implemented via Verilog Hardware description language (HDL). A test bench was created with a virtual AHB host and an optimized SRAM as the high-speed APB peripheral. Verdi simulation shows the bridge completely meets the design intention.