Design and Implementation of a Width-Adjustable Asynchronous FIFO for Cross-Clock Domain Data Transmission
DOI:
https://doi.org/10.61173/zweazt33Keywords:
Asynchronous fifo, Metastable state, Gray codeAbstract
Existing research shows that asynchronous FIFO has been widely used in a variety of complex system designs, such as FPGA-based image processing systems, USB communication systems, and so on. To make the designed asynchronous FIFO more programmable and flexible, so that it can adapt to various application scenarios more quickly, this paper studies and designs an asynchronous FIFO with adjustable input and output bit width. In this study, according to the relationship between 24-bit input data and 32-bit storage space, four 24-bit data are selected to fill three RAM storage spaces at one time. According to the multiple relationships between 32-bit storage space and 128-bit output data, the reading pointer is enlarged by 4 times to realize the function of reading four 32-bit data at one time. This whole process realizes the conversion of data bit width through data splicing. Finally, the 24-bit RGB888 image data is successfully converted into 128-bit data and transmitted to the bus, which successfully solves the problem of data width mismatch.References
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