RISC-V Leads the Future: Evolution and Outlook of CPU Architecture

Authors

  • Tongyan Yin
  • Zeqing Zhang
  • Tianqi Zhang

DOI:

https://doi.org/10.61173/sfv24n83

Keywords:

RISC-V, ArchitectureCPU, Performance Evaluation Pipeline Technology

Abstract

This essay mainly talked the development of CPU and some instruction set architecture based on RISCV. CPU is known as the Central Processing Unit, the main appliment is RISCV, Also the ARM architecture is characterized by a focus on the balance between low power consumption and high performance. Then X86, its significant advantage is its complex instruction set and excellent performance, so it can handle complex computational tasks. We also explore the Pipeline technology, it is a widely used parallel processing technology today. The design principle is to divide complex, multilevel combinational logic circuits into multiple levels. Then, we find some experiment data to explore our conclusion. We find that each has its own advantages and is better suited to different scenarios. In terms of performance, x86 offers superior capabilities but consumes more power, making it ideal for high-performance computing and server applications. ARM, on the other hand, excels in power efficiency and finds its primary use in mobile devices and embedded systems. RISC-V, known for its flexibility, allows for a balance between performance and power consumption based on specific requirements, making it suitable for highly customizable applications, IoT devices, and emerging high-performance computing markets. The advantages of each architecture in different fields depend on the specific application environment and demands placed on them.

References

[1] Hu Zhenbo Teach You how to Design CPU. RISC-V Processor Article Beijing: Posts and Telecommunications Press, 2018.6

[2] Wall Street observations-From boss to little brother,2024

[3] Roa Logic. RV12 RISC-V 32/64-bit CPU Core Datasheet (v1.3). Roa Logic B.V., 2018.

[4] Arm Limited. Introducing the Arm architecture. 2019 Arm Limited (or its affiliates). 2019.

[5] Tom Shanley. X86 Instruction Set Architecture. MindShare, Inc., 2009.

[6] GUO Shujun,WANG Yuhua. Application of pipeline technology in FPGA design[J]. Journal of Northern Polytechnic University,2004,(01):62-64+70.

[7] Chen Xian. An eight-stage pipeline structure design in CPU[D]. Xiangtan University,2018.

[8] Luo, Q., Kong, C., Cai, Y., Liu, G.: Performance evaluation of OpenMP constructs and kernel benchmarks on a Loongson-3A Quad-Core SMP system. In: 2011 12th International Conference on Parallel and Distributed Computing, Applications and Technologies, pp. 191–196 (2011)

[9] YuLiu, Kejiang Ye and Chengzhong Xu University o Academy of Sciencf Chinesees, Beijing 100049, Chinapp. 61– 74, 2022

[10] . SiFive, Inc.: SiFive FU740-C000 Manual (2021)

Downloads

Published

2024-10-29