Four-Bit Parallel Multiplier based on Digital Circuit Design

Abstract

This paper presents an investigation into a four-bit parallel multiplier based on an enhanced digital circuit design. The advent of computers and digital electronic systems has led to a significant increase in the importance of multiplication operations in a wide range of applications.In this paper, the circuit is designed using the Logisim, and the designed circuit is converted into a model and input into Modelsim for simulation. Finally, the feasibility of the circuit is verified through the Modelsim model. The objective of the circuit is to implement the multiplication operation of two four-bit inputs. The model designed in Logisim can facilitate the process of code writing in Modelsim simulations. Furthermore, once the simulation is complete, the simulation results can be compared with the circuit diagram to ascertain their alignment with reality. The entire model is based on the concept of a full adder, and the delay is reduced by disconnecting the serial feed chain, which results in a 25% reduction in delay compared to a full adder with two columns. This approach effectively achieves the desired reduction in delay.