Design and Optimization of the 4-Bit Absolute Value Logic Gate Circuits
DOI:
https://doi.org/10.61173/5hxfpz51Keywords:
Logic gate, 4-bit absolute value calculation, OptimizationAbstract
Absolute value computation of binary numbers has important applications in digital signal processing and arithmetic operations, but conventional circuit designs usually face high latency and energy consumption problems. In order to improve computational efficiency, this paper proposes an optimization method based on logic gate circuits aimed at reducing the number of physical components and simplifying the circuit structure. By using a truth table for logic simplification, a more efficient 4-bit absolute value calculation circuit is designed in this study. Experimental results show that the optimised circuit performs significantly in reducing latency and power consumption and maintains the accuracy of the operation. The results of the study provide a better implementation of digital circuit design for application scenarios that require efficient computation.
References
implementation and produces high latency. By simplify- [3] Dong, X., Jing, B., & Yang, X. (2021). Improved Design of ing these complex operations into a direct mapping which a 4-bit Absolute-Value Detector Using Simplified Chain Carry based on the truth table, the optimised circuit drastically Adder. Journal of Physics Conference Series, 2113(1), 012043. reduces the number of redundant logic gate layers and [4] Exploration of energy-delay tradeoffs in digital circuit connection paths. Thus reducing the power consumption design. (2008, March 1). IEEE Conference Publication | IEEE in the circuit. This optimisation method is not only use Xplore.
circuit resources more efficiently, but also improves the [5] Lin Shaoling. (2014). Optimal design of multi-cylinder dynamic performance of the circuit. Especially for appli- sequential electronic control system based on the truth table. In cations that need to process large-scale input data. The Journal of Mudanjiang University (p. Eleven).
optimized circuit can achieve a faster speed when it calcu- [6] Wei, Y. (2013). Study on complement codes of the negative. late the absolute value with a lower energy consumption. ELECTRONIC TEST, No12, 40–41.
This increase of efficiency makes optimal design not only [7] Wang, F. (2019). Step input auxiliary control for a class of applicable to simple logic operations, but also has the po- nonlinear systems. Journal of Wuhan Polytechnic University, tential to be generalised in the design of VLSI [10]. This 38(4), 1973–1995. optimization fully reflects the necessity and effectiveness [8] Shi Zhanhua, He Lijuan, Liang Xiaoqing, & Zhang Xiaojuan.
of this design optimization. (2022). Analysis and simulation of combinational logic circuits based on Multisim10.0. ELECTRONICS WORLD. 6. Conclusion [9] Yang, G. (2023). Optimized design of a 4-bits absolute-value This paper successfully proposes a optimized logic gate detector. Highlights in Science, Engineering and Technology, 31, method of the design of 4-bit absolute value circuits, 224–231.
aiming at reducing latency and energy consumption. The [10] Rawat, A., & Kumar, A. (2013). Designing issues associated circuit performance has been significantly improved, by with very large scale integrated circuits designing issues changing the traditional subtracter and inverse circuit de- associated with very large scale integrated circuits. International sign method to a simplified design which is based on the Journal of Computer Science and Technology, 4. direct logic of truth table. Because of reducing number
Downloads
Published
Issue
Section
License
Copyright (c) 2024 by the authors.

This work is licensed under a Creative Commons Attribution 4.0 International License.
