Design and Implementation of Digital Integrated Circuit Based Frequency Dividers
DOI:
https://doi.org/10.61173/94edr597Keywords:
fractional frequency division, digital integrated circuit, simulation experimentAbstract
This research aims to research the basic fractional frequency division. This article first introduces the theory of the dualmode prescaler method, and then use this method to calculate the number of integer frequency divisions and show that how to achieve the target fractional division ratio. after that, Verilog code is used to implement fractional frequency division, and using simulation to show the operation of the divider. The simulation shows that the designed fractional frequency divider can be implemented by evenly inserting different values of integer frequency dividers. However, the experiment in this article may has time error in the output signal, because the accurate 50% duty cycle cannot be achieved. In addition, the frequency division period is not completely uniform. Finally, the challenges and limitations of fractional frequency division technology in theory and practice will be summarized.
References
[1] Wang, Y., Chi, M.-H., Jesse Jen-Chung Lou, & Chen, C.- Z. (2023). Handbook of Integrated Circuit Industry (pp. 3–24). Springer Nature.
[2] Arai, K., Kapoor, S., & Bhatia, R. (2020). Proceedings of the Future Technologies Conference (FTC) 2020, Volume 2 (pp. 340–346). Springer Nature.
[3] Mohamed Samy El-Daleel. (2023). A Fully Linear PLL for Power Electronics Applications and PLL Tuning Guidelines Along with Comparative Study of Different Phase Detection Methods. 2023 IEEE Conference on Power Electronics and Renewable Energy (CPERE). IEEE Xplore. https://doi. org/10.1109/cpere56564.2023.10119579
[4] Zheng, Y., & Chen, X. (2023). A Low-Power RF programmable frequency divider. https://doi.org/10.1109/ icccs57501.2023.10150629
[5] Dong, C., Dong, G., & Hu, S. (2020). A 5G Millimeter Low Power Phase-Locked Loop in Low-Cost 0.18-μm CMOS. 2020 IEEE MTT-S International Wireless Symposium (IWS). https:// doi.org/10.1109/iws49314.2020.9360063
[6] Best, R. (2003). Phase-Locked Loops (pp. 103–107). McGraw Hill Professional.
[7] Cheung, T. H., Ryynanen, J., Parssinen, A., & Stadius, K. (2021). A 5.4-GHz 2/3/4-Modulus Fractional Frequency Divider Circuit in 28-nm CMOS. 2021 IEEE International Symposium on Circuits and Systems (ISCAS). https://doi.org/10.1109/ iscas51556.2021.9401405
[8] Nicola Da Dalt, & Sheikholeslami, A. (2018). Understanding Jitter and Phase Noise (pp. 111–120). Cambridge University Press.
[9] Cheung, T., Martelius, M., Antonov, Y., Akbar, R., Ryynänen, J., Pärssinen, A., & Stadius, K. (n.d.). A 3.5-GHz Digitally- Controlled Open-Loop Fractional-N Frequency Divider in 28- nm CMOS.
[10] Zheng, Y., & Chen, X. (2023). A Low-Power RF programmable frequency divider. https://doi.org/10.1109/ icccs57501.2023.10150629
Downloads
Published
Issue
Section
License
Copyright (c) 2024 by the authors.
This work is licensed under a Creative Commons Attribution 4.0 International License.
