Research on Latch-up effect suppression method of IC based on CMOS technology
DOI:
https://doi.org/10.61173/av9efx49Keywords:
CMOS integrated circuit, latch-up effect, suppression methods, layout design, process optimizationAbstract
Latch-up effect is a kind of parasitic effect in CMOS integrated circuits. Taking CMOS inverter as an example, this paper analyzes the formation mechanism of latch-up effect in CMOS integrated circuits, deduces the trigger conditions of latch-up effect by establishing equivalent circuit models, introduces the methods of suppressing latch-up effect from layout design and process optimization, and finally conducts simulation test to verify the effect of suppression methods.
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